1. Field of the Invention
The present invention relates to a test apparatus and test method for an electronic device. Particularly, the present invention relates to a test apparatus and test method for testing a memory under test which stores, in each of its pages, a data sequence affixed with an error check and correction.
2. Relate Art
A test apparatus for a semiconductor memory logically compares an output from a memory under test with an expectation value in each test cycle, and detects the memory as having passed the test in a case where the compared values match each other while detects it as having failed if they do not match. Hence, if only one failure at all is detected from such kind of memory under test as a flash memory, from which its stored data is read out in the unit of page in one cycle after another, and which is affixed with an error check and correction in each of its pages, this memory under test is detected as defective as well.
Here, a flash memory might have an impermanent soft error, with a program disturbing mode occurring to force data to be rewritten in the storage cells other than those secured for writing data. See a non-patent literature 1 given below, as for the occurrence of such an error. If such a software error occurs in an actual use, the memory controller that controls the flash memory corrects the error in the data read out from the flash memory.
Thus, in a test on a flash memory, if an error within the limit in which errors can be corrected with an error check and correction occurs, this memory under test should be judged as an article that can pass the test. However, it should be noted that some flash memories may be liable to have errors due to software errors as described above while other flash memories may not include even a defect of 1 bit. Hence, someone might request that flash memories that can operate normally be classified according to how safe they are from occurrence of errors, in order to determine their applications or their prices when sold.
[Non-Patent Literature 1] Koji Sakuta, ‘Large-capacity NAND flash memory techniques for the age of Silicon Movie’, FED Journal, Vol. 11, No. 3, 2000, pp. 76-88
In order that flash memories may be classified according to how safe they are from occurrence of errors, the number of errors which occur in each page is counted page by page, and this count number is judged as to whether it meets a predetermined quality standard. A repair process for replacing defective storage cells with spare storage cells is given to any pages that do not satisfy the quality standard. If any flash memory reaches the quality standard after the repair process, it will be classified into the grade corresponding to the quality standard.
In order to enable this classification, it is a possible way to acquire from the test apparatus data for all storage cells included in all pages about whether they have passed or failed and analyze the data by human labor or by computer. However, analyses cost much labor and time since there are an enormous number of storage cells. Some of the acquired data may be found useless because some pages have originally met the quality standard and require no repair process.